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fedl620q150a-01 issue date: may 7, 2015 ml620q151a/2a/3a/4a/5a/6a/7a/8a/9a 16-bit micro controller 1/36 general description this lsi is a high-performance 16-bit cmos microcontroller into which rich peripheral circuits, such as 10-bit a/d converter, timer, pwm, synchronous serial port, uart, i2c bus interface (master), low level de tect circuit, are inco rporated around 16-bit cpu nx-u16/100. the cpu nx-u16/100 is capable of efficien t instruction execution in 1-instruction 1-clock mode by 3-stage pipe line architectur e parallel procesing. and, this lsi has a data flash-memory fill area by a software which can be written in. in addition, it has an on-chip debugging function, which allows software de bugging/rewriting with the lsi mounted on the board. features ? cpu ? 16-bit risc cpu (cpu name: nx-u16/100) ? instruction system:16-bit instructions ? instruction set:transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on ? on-chip debug function ? minimum instruction execution time approx 30.5 s (at 32.768khz system clock) approx 0.122 s (at 8.192mhz system clock) ? internal memory ? flash-memory product program area rewrite cycle ml620q151a/ML620Q154A/ml620q157a 32-kbyte* (16k 16-bit) ml620q152a/ml620q155a/ml620q158a 48-kbyte* (24k 16-bit) ml620q153a/ml620q156a/ml620q159a 64-kbyte* (32k 16-bit) 100 * including unusable 1kbyte test area internal 2-kbyte data flash (1-kbyte 2) rewrite cycle: 10,000 times ? sram: internal 2-kbyte ram (2-kbyte 8 -bits) ? interrupt controller ? 2 non-maskable interrupt sources (internal source: back-up clock, wdt) ? maskable interrupt product interrupt source ml620q151a/ML620Q154A/ml620q157a 27 (internal source: 20, external source: 7) ml620q152a/ml620q155a/ml620q158a 28 (internal source: 20, external source: 8) ml620q153a/ml620q156a/ml620q159a 28 (internal source: 20, external source: 8) ? 4 steps of interrupt level, and a mask function
fedl620q150a-01 ml620q151a/2a/3a/4a/5a/6a/7a/8a/9a 2/36 ? time base counter ? low-speed time base counter 1 channel ? watchdog timer ? generates a non-maskable interrupt upon the first overflow and a system reset occurs upon the second ? free running ? overflow period: 4 types selectable (125ms, 500ms, 2s, 8s @32.768khz) ? timers ? 8 bits 2ch (16-bits configuration available 1ch) ? 16 bits 4ch ? pwm ? 16bits 4ch ? the auto reload timer mode / pwm mode ? timer start-stop function by the software and an external trigger. ? a pulse width can be measured using an external-trigger input. ? an external event can be selected as the counter clock. ? complement synchronous pwm ? synchronous serial port ? 1ch ? master/slave selectable ? lsb first/msb first selectable ? 8-bit length/16-bit length selectable ? uart ? full-duplex 1ch ( half-duplex 2ch ) ? bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits ? positive logic/negative logic selectable ? built-in baud rate generator ? i 2 c bus interface ? master function only ? fast mode (400kbit/s), standard mode (100kbit/s) ? successive approximation type a/d converter ? 10-bit a/d converter ? input: 12ch maximum ? conversion time: 43us, 13.5 s per channel (conversion-time is selectable) ? analog comparator ? 1ch ? edge for the interrupt and sampling function is selectable.
fedl620q150a-01 ml620q151a/2a/3a/4a/5a/6a/7a/8a/9a 3/36 ? general-purpose ports including secondary functions ? input-only ports input-only ports (including multiple functions) product when not using the crystal resonator when using the crystal resonator ml620q151a/ml620q152a/ml620q153a 6ch 5ch ML620Q154A/ml620q155a/ml620q156a 7ch 6ch ml620q157a/ml620q158a/ml620q159a 7ch 6ch ? output-only ports : 4ch ? input/output ports input/output ports (including multiple functions) product when not using the crystal resonator when using the crystal resonator ml620q151a/ml620q152a/ml620q153a 31ch 30ch ML620Q154A/ml620q155a/ml620q156a 34ch 33ch ml620q157a/ml620q158a/ml620q159a 46ch 45ch ? reset ? reset through the reset_n pin ? power-on reset generation when powered on ? reset by the watchdog timer (wdt) overflow ? reset by the low level detector (lld) ? low level detect function ? threshold voltages: 4values (1.9v/2.55v/3.7v/4.2v) a threshold voltage is selected as code-option. ? lld is a ready as a supply-voltage supervisory reset. reset or an interrupt output is selectable as code-option. ? clock ? low-speed clock (this lsi can not guarantee the operation without low-speed clock) crystal oscillation (32.768 khz) or built-in rc oscillation (32.768khz) crystal oscillation or built-in rc oscilla tion is selectable as code-option. ? high-speed clock built-in rc oscillation (2.097mhz) or built-in pll oscillation (8.192mhz) ? power management ? halt mode: instruction execution by cpu is suspende d (peripheral circuits are in operating states). ? stop mode: stop of low-speed oscillation and high-speed oscillation (operations of cpu and peripheral circuits are stopped.) ? clock gear: the frequency of high-speed system clock can be ch anged by software (1/1, 1/2, 1/4, or 1/8 of the oscillation clock) ? block control function: operation of an intact functional block circuit is powerd down. (register reset and clock stop)
fedl620q150a-01 ml620q151a/2a/3a/4a/5a/6a/7a/8a/9a 4/36 ? package product package ml620q151a/ml620q152a/ml620q153a 48pintqfp (p-tqfp48-0707-0.50-qk) ML620Q154A/ml620q155a/ml620q156a 52pintqfp (p-tqfp52-1010-0.65-tk) ml620q157a/ml620q158a/ml620q159a 64pinqfp (p-qfp64-1414-0.80-uk) ? guaranteed operating range ? operating temperature: ? 40 c to +105 c ? operating voltage: v dd = 1.8v to 5.5v the difference point of this lsi is shown below. function ml620q151a/152a/153a ml620q 154a/155a/156a ml620q157a/158a/159a shipment 48pintqfp 52pintqfp 64pinqfp flash capacity (program area) 32kbyte(ml620q151a) 48kbyte(ml620q152a) 52kbyte(ml620q153a) 32kbyte(ML620Q154A) 48kbyte(ml620q155a) 52kbyte(ml620q156a) 32kbyte(ml620q157a) 48kbyte(ml620q158a) 52kbyte(ml620q159a) maskable interrupt 27 28 28 input-only port (at the case of crystal unused) 6 7 7 p05 port ? available available input/output port (at the case of crystal unused) 31 34 46 p36,p53,p64 ports ? available available p37 port ? ? available p50 p52 ports ? ? available p65 p67 ports ? ? available p70 p74 ports ? ? available :none
fedl620q150a-01 ml620q151a/2a/3a/4a/5a/6a/7a/8a/9a 5/36 block diagram block diagram of ml620q151a/ml620q152a/ml620q153a(tqfp48) figure 1-1 block diagram of ml620q151a/ml620q152a/ml620q153a(tqfp48) program memory (flash) 32/48/64kbyte ram 2kbyte interrupt controller cpu ( nx-u16/100 ) timing controlle r ea sp on-chip ice instruction decode r bus controller instruction re g iste r tbc int 4 int 1 wdt 8bit timer 2 16bit timer 4 int 4 16bittimer with pwmx4 gpio int 7 data-bus test 0 * 3 reset n osc xt0 xt1 lsclk* outclk* power v ddl reset & test alu epsw1 ? 3 psw elr1 ? 3 lr ecsr1 ? 3 dsr/csr pc greg 0 ? 15 v dd v ss analog comparator 1 cmp0p cmp0m int 1 sa-adc int 1 ain0 to ain11 v ref v dd test1_n pw45ev1* pw45ev0* pw67ev0* pw67ev1* tmhaout* int 6 tmhbout* pwm4* pwm5* pwm6* lld i2cx1 sda0* int 1 scl0* uartx1 (*1) rxd0* int 2 txd0* rxd1* txd1* ssiox1 sck0* int 1 sin0* sout0* p00 to p04 p12* 2 p13* 2 p14* 3 p20 to p23 p30 to p35 p40 to p47 p54 to p57 p60 to p63 p80 to p87 int 1 int 1 pwm7* * secondary or tertiary or quaternary function * 1 full-duplex 1ch ( half-duplex 2ch ) * 2 cannot be used as i/o port when connecting the crystal resonator * 3 cannot be used as i/o port when c onnecting the uease(on-chip debug emualtor)
fedl620q150a-01 ml620q151a/2a/3a/4a/5a/6a/7a/8a/9a 6/36 block diagram of ML620Q154A/ml620q155a/ml620q156a(tqfp52) figure 1-2 block diagram of ML620Q154A/ml620q155a/ml620q156a(tqfp52) program memory (flash) 32/48/64kbyte ram 2kbyte interrupt controller cpu ( nx-u16/100 ) timing controlle r ea sp on-chip ice instruction decode r bus controller instruction re g iste r tbc int 4 int 1 wdt 8bit timer 2 16bit timer 4 int 4 16bittimer with pwmx4 int 8 data-bus test 0 * 3 re s et n osc xt0 xt1 lsclk* outclk* power v ddl reset & test alu epsw1 ? 3 psw elr1 ? 3 lr ecsr1 ? 3 dsr/csr pc greg 0 ? 15 v dd v ss analog comparator 1 cmp0p cmp0m int 1 sa-adc int 1 ain0 to ain11 v ref v dd test1_n pw45ev1* pw45ev0* pw67ev0* pw67ev1* tmhaout* int 6 tmhbout* pwm4* pwm5* pwm6* lld i2cx1 sda0* int 1 scl0* uartx1 (*1) rxd0* int 2 txd0* rxd1* txd1* ssiox1 sck0* int 1 sin0* sout0* int 1 int 1 pwm7* gpio p00 to p05 p12* 2 p13* 2 p14* 3 p20 to p23 p30 to p36 p40 to p47 p54 to p57 p60 to p64 p80 to p87 * secondary or tertiary or quaternary function * 1 full-duplex 1ch ( half-duplex 2ch ) * 2 cannot be used as i/o port when connecting the crystal resonator * 3 cannot be used as i/o port when c onnecting the uease(on-chip debug emualtor)
fedl620q150a-01 ml620q151a/2a/3a/4a/5a/6a/7a/8a/9a 7/36 block diagram of ml620q157a/ml620q158a/ml620q159a(qfp64) figure 1-3 block diagram of ml620q157a/ml620q158a/ml620q159a(qfp64) program memory (flash) 32/48/64kbyte ram 2kbyte interrupt controller cpu ( nx-u16/100 ) timing controlle r ea sp on-chip ice instruction decode r bus controller instruction re g iste r tbc int 4 int 1 wdt 8bit timer 2 16bit timer 4 int 4 16bittimer with pwmx4 int 8 data-bus test 0 * 3 re s et n osc xt0 xt1 lsclk* outclk* power v ddl reset & test alu epsw1 ? 3 psw elr1 ? 3 lr ecsr1 ? 3 dsr/csr pc greg 0 ? 15 v dd v ss analog comparator 1 cmp0p cmp0m int 1 sa-adc int 1 ain0 to ain11 v ref v dd test1_n pw45ev1* pw45ev0* pw67ev0* pw67ev1* tmhaout* int 6 tmhbout* pwm4* pwm5* pwm6* lld i2cx1 sda0* int 1 scl0* uartx1 (*1) rxd0* int 2 txd0* rxd1* txd1* ssiox1 sck0* int 1 sin0* sout0* int 1 int 1 pwm7* gpio p00 to p05 p12* 2 p13* 2 p14* 3 p20 to p23 p30 to p37 p40 to p47 p54 to p57 p60 to p64 p70 to p74 p80 to p87 * secondary or tertiary or quaternary function * 1 full-duplex 1ch ( half-duplex 2ch ) * 2 cannot be used as i/o port when connecting the crystal resonator * 3 cannot be used as i/o port when c onnecting the uease(on-chip debug emualtor)
fedl620q150a-01 ml620q151a/2a/3a/4a/5a/6a/7a/8a/9a 8/36 pin configuration ml620q151a/ml620q152a/ml620q153a tqfp48 package product figure 1-4 pin layout of ml620q151a/ml620q152a/ml620q153a tqfp48 package 12 1 2 3 4 5 6 7 8 9 10 11 26 27 28 29 30 31 32 33 34 35 36 24 23 22 21 20 19 18 17 16 15 14 39 40 41 42 43 44 45 46 47 37 p32/ain2/pw45ev0 p30/exi6/ain0/pw45ev1 p31/exi7/ain1/pw67ev1 v dd v ref p35/ain5/pwm5 p34/ain4/pwm4 p33/ain3/pw67ev0 p45/ain9/t1p5ck/sck0 p46/ain10/t16ck0/sout0 p00/exi0/pw45ev0 p01/exi1/pw67ev0 p02/exi2/rxd0 p04/exi4 p03/exi3/rxd1 p44/ain8/t0p4ck/sin0 p43/ain7/txd0/pwm4/txd1 p42/ain6/rxd0/sout0 p41/scl/sck0/cmp0p p47/ain11/t16ck1/pwm5 p54/rxd0 p20/led0/lsclk/pwm4 p21/led1/outclk/pwm5 p22/led2/tmhaout/pwm6 p14/test0 reset_n 38 p55/txd0/sin0/txd1 v ss p56/sck0 p57/sout0/pwm7 p63/pw67ev1 p62/pw45ev1 v ddl p82/sout0 p61/scl/tmhbout/pwm7 p87/txd0/pwm4 p83/pwm5 p84/rxd1/sin0 p85/txd1/sck0 p86/rxd0/sout0 p13/xt1 p12/xt0 p80/sda/sin0 p81/scl/sck0 (top view) tqfp48 25 13 p40/sda/sin0/cmp0m 48 test1_n p60/sda/tmhaout/pwm6 p23/led3/tmhbout/pwm7
fedl620q150a-01 ml620q151a/2a/3a/4a/5a/6a/7a/8a/9a 9/36 ML620Q154A/ml620q155a/ml620q156a tqfp52 package product figure 1-5 pin layout of ML620Q154A/ml620q155a/ml620q156a tqfp52 package 12 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31 32 33 34 35 36 37 38 39 26 25 24 23 22 21 20 19 18 17 16 15 42 43 44 45 46 47 48 49 50 51 40 p32/ain2/pw45ev0 p64/pwm4 p30/exi6/ain0/pw45ev1 p31/exi7/ain1/pw67ev1 v dd v ref p35/ain5/pwm5 p34/ain4/pwm4 p33/ain3/pw67ev0 p45/ain9/t1p5ck/sck0 p46/ain10/t16ck0/sout0 p00/exi0/pw45ev0 p01/exi1/pw67ev0 p02/exi2/rxd0 p04/exi4 p05/exi5 p03/exi3/rxd1 p44/ain8/t0p4ck/sin0 p43/ain7/txd0/pwm4/txd1 p42/ain6/rxd0/sout0 p41/scl/sck0/cmp0p p47/ain11/t16ck1/pwm5 p53/txd1/pwm6 p20/led0/lsclk/pwm4 p21/led1/outclk/pwm5 p22/led2/tmhaout/pwm6 p23/led3/tmhbout/pwm7 p14/test0 reset_n 41 p54/rxd0 v ss p55/txd0/sin0/txd1 p56/sck0 p57/sout0/pwm7 p63/pw67ev1 p62/pw45ev1 v ddl p82/sout0 p61/scl/tmhbout/pwm7 p87/txd0/pwm4 p83 /pwm5 p84/rxd1/sin0 p85/txd1/sck0 p86 /rxd0/sout0 p13/xt1 p12/xt0 p80/sda/sin0 p81/scl/sck0 (top view) tqfp52 27 14 p40/sda/sin0/cmp0m 52 test1_n 13 p36/lsclk p60/sda/tmhaout/pwm6
fedl620q150a-01 ml620q151a/2a/3a/4a/5a/6a/7a/8a/9a 10/36 ml620q157a/ml620q158a/ml620q159a qfp64 package product figure 1-6 pin layout of ml620q157a/ml620q158a/ml620q159a qfp64 package 12 1 2 3 4 5 6 7 8 9 10 11 34 35 36 37 41 42 43 44 45 46 47 48 32 31 30 29 28 24 23 22 21 20 19 18 p32/ain2/pw45ev0 p64/pwm4 p30/exi6/ain0/pw45ev1 p31/exi7/ain1/pw67ev1 v dd v ref p35/ain5/pwm5 p34/ain4/pwm4 p33/ain3/pw67ev0 p45/ain9/t1p5ck/sck0 p46/ain10/t16ck0/sout0 p44/ain8/t0p4ck/sin0 p43/ain7/txd0/pwm4/txd1 p42/ain6/rxd0/sout0 p41/scl/sck0/cmp0p p47/ain11/t16ck1/pwm5 p53/txd1/pwm6 p54/rxd0 v ss p55/txd0/sin0/txd1 p56/sck0 p57/sout0/pwm7 p63/pw67ev1 p62/pw45ev1 v ddl p82/sout0 p61/scl/tmhbout/pwm7 p87/txd0/pwm4 p83 /pwm5 p84/rxd1/sin0 p85/txd1/sck0 p86 /rxd0/sout0 p13/xt1 p12/xt0 p80/sda/sin0 p81/scl/sck0 (top view) qfp64 33 17 p40/sda/sin0/cmp0m 13 p36/lsclk p60/sda/tmhaout/pwm6 15 14 p70/pwm6 p37/outclk 16 p71/pwm7 27 26 25 p50/sda/sin0 p51/scl/sck0 p52/rxd1/sout0 38 39 40 p67 p66/outclk/pwm6 p65/lsck/pwm5 49 50 51 52 53 54 55 56 57 58 62 63 64 59 60 61 test1_n reset_n p14/test0 p74/sout0 p73/txd1/sck0/txd0 p72/rxd1/sin0 p05/exi5 p21/led1/outclk/pwm5 p00/exi0/pw45ev0 p01/exi1/pw67ev0 p02/exi2/rxd0 p03/exi3/rxd1 p04/exi4 p20/led0/lsclk/pwm4 p22/led2/tmhaout/pwm6 p23/led3/tmhbout/pwm7
fedl620q150a-01 ml620q151a/2a/3a/4a/5a/6a/7a/8a/9a 11/36 list of pins primary function secondary function te rtiary function quaternary function 48 pin no. 52 pin no. 64 pin no. pin name i/o description pin name i/o de- scription pin name i/o de- scription pin name i/o de- scription 3 3 3 vss ? negative power supply pin ? ? ? ? ? ? ? ? ? 5 5 5 v dd ? positive power supply pin ? ? ? ? ? ? ? ? ? 4 4 4 v ddl ? power supply for internal logic (internally generated) ? ? ? ? ? ? ? ? ? 46 50 62 p14/ test0 i input port/ input pin for testing ? ? ? ? ? ? ? ? ? 47 51 63 reset_n i reset input pin ? ? ? ? ? ? ? ? ? 48 52 64 test1_n i input pin for testing ? ? ? ? ? ? ? ? ? 1 1 1 p12/ xt0 i input port/ low-speed clock oscillation pin ? ? ? ? ? ? ? ? ? 2 2 2 p13/ xt1 i/o input/output port/ low-speed clock oscillation pin ? ? ? ? ? ? ? ? ? 6 6 6 v ref ? reference power supply pin of successive-approxi mation type adc ? ? ? ? ? ? ? ? ? 37 40 49 p00/exi0/ pw45ev0 i input port / external interrupt / pw45ev0 input ? ? ? ? ? ? ? ? ? 38 41 50 p01/exi1/ pw67ev0 i input port / external interrupt / pw67ev0 input ? ? ? ? ? ? ? ? ? 39 42 51 p02/exi2/ rxd0 i input port / external interrupt uart0 data input ? ? ? ? ? ? ? ? ? 40 43 52 p03/exi3/ rxd1 i input port / external interrupt uart1 data input ? ? ? ? ? ? ? ? ? 41 44 53 p04/exi4 i input port / external interrupt ? ? ? ? ? ? ? ? ? ? 45 54 p05/exi5 i input port / external interrupt ? ? ? ? ? ? ? ? ? 42 46 55 p20/ led0/ o output port / led drive lsclk ? ? ? 43 47 56 p21/ led1/ o output port / led drive outclk ? ? ? 44 48 57 p22/ led2/ o output port / led drive ? ? ? tmhao ut o timera output pwm6 45 49 58 p23/ led3/ o output port / led drive ? ? ? tmhbo ut o timerb output pwm7 7 7 7 p30/exi6 pw45ev1/ ain0 i/o input/output port / pw45ev1 input / successive approximation type adc input ? ? ? ? ? ? ? ? ? 8 8 8 p31/exi7 pw67ev1/ ain1 i/o input/output port / pw67ev1 input / successive approximation type adc input ? ? ? ? ? ? ? ? ? 9 9 9 p32/ pw45ev0/ ain2 i/o input/output port / pw45ev0 input / successive approximation type adc input ? ? ? ? ? ? ? ? ? 10 10 10 p33/ pw67ev0/ ain3 i/o input/output port / pw67ev0 input / successive approximation type ? ? ? ? ? ? ? ? ?
fedl620q150a-01 ml620q151a/2a/3a/4a/5a/6a/7a/8a/9a 12/36 primary function secondary function te rtiary function quaternary function 48 pin no. 52 pin no. 64 pin no. pin name i/o description pin name i/o de- scription pin name i/o de- scription pin name i/o de- scription adc input 11 11 11 p34/ ain4/ i/o input/output port / successive approximation type adc input ? ? ? pwm4 o pwm4 output ? ? ? 12 12 12 p35/ ain5/ i/o input/output port / successive approximation type adc input ? ? ? pwm5 o pwm5 output ? ? ? ? 13 13 p36 i/o input/output port lsclk ? ? ? ? ? ? ? ? 14 p37 i/o input/output port outclk ? ? ? ? ? ? 13 14 17 p40/ cmp0m i/o input/output port / comparator0 inverting input sda i/o i 2 c data input/ou tput sin0 i ssio0 data input ? ? ? 14 15 18 p41/ cmp0p i/o input/output port / comparator0 non-inverting input scl i/o i 2 c clock input/ou tput sck0 i/o ssio0 synchron ous clock input/out put ? ? ? 15 16 19 p42/ ain6 i/o input/output port / successive approximation type adc input rxd0 i uart0 data input sout0 o ssio0 data output ? ? ? 16 17 20 p43/ ain7 i/o input/output port / successive approximation type adc input txd0 o uart0 data output pwm4 o pwm4 output txd1 o uart1 data output 17 18 21 p44/ t0p4ck/ ain8 i/o input/output port / pwm4 external clock input/ successive approximation type adc input ? ? ? sin0 i ssio0 data input ? ? ? 18 19 22 p45/ t1p5ck/ ain9 i/o input/output port / pwm5 external clock input/ successive approximation type adc input ? ? ? sck0 i/o ssio0 synchron ous clock input/out put ? ? ? 19 20 23 p46/ t16ck0/ ain10 i/o input/output port / timer8,a / pwm6 external clock input / successive approximation type adc input ? ? ? sout0 o ssio0 data output ? ? ? 20 21 24 p47/ t16ck1/ ain11 i/o input/output port / timer9,b / pwm7 external clock input / successive approximation type adc input ? ? ? pwm5 o pwm5 output ? ? ? ? ? 25 p50 i/o input/output port sda i/o ? ? 26 p51 i/o input/output port scl i/o sck0 i/o ssio0 synchron ous clock input/out put ? ? 27 p52 i/o input/output port rxd1 i uart1 data input sout0 o ssio0 data output
fedl620q150a-01 ml620q151a/2a/3a/4a/5a/6a/7a/8a/9a 13/36 primary function secondary function te rtiary function quaternary function 48 pin no. 52 pin no. 64 pin no. pin name i/o description pin name i/o de- scription pin name i/o de- scription pin name i/o de- scription ? 22 28 p53 i/o input/output port txd1 o uart1 data output pwm6 o pwm6 output ? ? ? 21 23 29 p54 i/o input/output port rxd0 i uart0 data input ? ? ? ? ? ? 22 24 30 p55 i/o input/output port txd0 o i ssio0 data input txd1 o 23 25 31 p56 i/o input/output port ? ? ? sck0 i/o ? ? ? 24 26 32 p57 i/o input/output port ? ? ? sout0 pwm7 25 27 33 p60 i/o input/output port sda i/o i/o tmhbo ut o timerb output pwm7 o pwm7 output 27 29 35 p62/ pw45ev1 i/o input/output port / pw45ev1 input ? ? ? ? ? ? ? ? ? 28 30 36 p63/ pw67ev1 i/o input/output port / pw67ev1 input ? ? ? ? ? ? ? ? ? ? 31 37 p64 i/o input/output port ? ? ? pwm4 o pwm4 output ? ? ? ? ? 38 p65 i/o input/output port lsclk ? ? ? ? ? 39 p66 i/o input/output port outclk ? ? ? ? ? 40 p67 i/o input/output port ? ? ? ? ? ? ? ? ? ? ? 15 p70 i/o input/output port ? ? ? pwm6 o pwm6 output ? ? ? ? ? 16 p71 i/o input/output port ? ? ? pwm7 o pwm7 output ? ? ? ? ? 59 p72 i/o input/output port rxd1 i uart1 data input sin0 i ssio0 data input ? ? ? ? ? 60 p73 i/o input/output port txd1 o o ? ? 61 p74 i/o input/output port ? ? ? sout0 o ssio0 data output ? ? ? 29 32 41 p80 i/o input/output port sda i/o sin0 i ssio0 data input ? ? ? 30 33 42 p81 i/o input/output port scl i/o sck0 i/o ? ? ? 31 34 43 p82 i/o input/output port ? ? ? sout0 ? ? ? 32 35 44 p83 i/o input/output port ? ? ? pwm5 o ? ? ? 33 36 45 p84 i/o input/output port rxd1 i uart1 data sin0 i ssio0 data ? ? ?
fedl620q150a-01 ml620q151a/2a/3a/4a/5a/6a/7a/8a/9a 14/36 primary function secondary function te rtiary function quaternary function 48 pin no. 52 pin no. 64 pin no. pin name i/o description pin name i/o de- scription pin name i/o de- scription pin name i/o de- scription input input 34 37 46 p85 i/o input/output port txd1 o ? ? ? 35 38 47 p86 i/o input/output port rxd0 i uart0 data input sout0 o ssio0 data output ? ? ? 36 39 48 p87 i/o input/output port txd0 o o ? ? ?
fedl620q150a-01 ml620q151a/2a/3a/4a/5a/6a/7a/8a/9a 15/36 pin description pin name i/o description primary/ secondary/ tertiary/ quaternary logic power supply v ss ? negative power supply pin ? ? v dd ? positive power supply pin ? ? v ddl ? positive power supply pin for internal logic (internally generated). connect capacitors (c l ) (see measuring circuit 1) between this pin and v ss . ? ? test test0 i input/output pin for testing. ? positive test1_n i input/output pin for testing. this pi n has a pull-up resistor built in. ? negative system reset_n i reset input pin. when this pin is set to a ? l ? level, the device is placed in system reset mode and the internal circuit is initia lized. if after that this pin is set to a ? h ? level, program execution starts. this pin has a pull-up resistor built in. ? negative xt0 i ? ? xt1 o crystal connection pin for low-speed clock. a 32.768 khz crystal oscillator (see measuring circuit 1) is connected to this pin. capacitors cdl and cgl are connected across this pin and vss as required. ? ? lsclk* o low-speed clock output. this function is al located to the second ary function of the p20/p36/p65 pin. secondary ? outclk* o high-speed clock output. this function is allocated to the secondary function of the p21/p37/p66 pin. secondary ? general-purpose input port p00 to p05* i p12 i p13 i/o p14 i general-purpose input or output ports. primary positive general-purpose output port p20 to p23 o general-purpose out put ports. provided with a secondary or tertiary or quaternary function for each port. cannot be used as ports if their secondary functions or tertiary or quaternary are used. secondary/ tertiary/ quaternary positive general-purpose input/output port p30 to p37* p40 to p47 p50 to p57* p60 to p67* p70 to p74* p80 to p87 i/o general-purpose output ports. provided with a secondary or tertiary or quaternary function for each port. cannot be used as ports if their secondary functions or tertiary or quaternary are used. secondary/ tertiary/ quaternary positive *: ml620q15xa have a different pin configuration for eac h package. see ?list of pins? for more details. pin name i/o description primary/ secondary/ tertiary/ logic
fedl620q150a-01 ml620q151a/2a/3a/4a/5a/6a/7a/8a/9a 16/36 quaternary uart txd0* o uart0 data output pin. alloca ted to the secondary func tion of the p43, p55 , p87 and the fourthly function of the p73. secondary quaternary positive rxd0* i uart0 data input pin. allocated to t he secondary function of the p02, p42, p54 and p86. secondary positive txd1* o uart1 data output pin. alloca ted to the secondary function of the p53, p73, p85, and the fourthly f unction of the p43, p55. secondary quaternary positive rxd1* i uart1 data input pin. allocated to t he secondary function of the p03, p52, p72 and p84. secondary positive i 2 c bus interface sda* i/o i 2 c data input/output pin. this pin is us ed as the secondary function of the p40, p50, p60 and p80. this pi n has an nmos open drain output. when using this pin as a function of the i 2 c, externally connect a pull-up resistor. secondary positive scl* i/o i 2 c clock output pin. this pin is used as the secondary func tion of the p41, p51, p61 and p81. this pin has an nm os open drain output. when using this pin as a function of the i 2 c, externally connect a pull-up resistor. secondary positive synchronous serial (ssio) sin0* i synchronous serial data input pin. allo cated to the tertiary function of the p40, p44, p50, p55, p72, p80 and p84. tertiary positive sck0* i/o synchronous serial clock input/output pin. allocated to the tertiary function of the p41, p45, p51, p 56, p73, p81 and p85. tertiary ? sout0* o synchronous serial data output pin. allo cated to the tertiary function of the p42, p46, p52, p57, p74, p82 and p86. tertiary positive pwm pwm4* o pwm4 output pin. allocated to the tertia ry function of the p34, p43, p64 and p87. tertiary positive pwm5* o pwm5 output pin. allocated to the tertia ry function of the p35, p47, p65 and p83. tertiary positive pwm6* o pwm6 output pin. allocated to the tertia ry function of the p53, p66, p70 and fourthly function of the p22 and p60. tertiary quaternary positive pwm7* o pwm7 output pin. allocated to the tert iary function of the p71 and fourthly function of the p23, p57, and p61. tertiary quaternary positive pw45ev0 pw45ev1 i control start /stop/clear for pwm4 and pwm5. allocated to the primary function of the p00, p30, p32 and p62. primary ? pw67ev0 pw67ev1 i control start /stop/clear pin for pwm6 and pwm7. allocated to the primary function of the p01, p31, p33, and p63. primary ? t0p4ck i external clock input pin for timer 0 and pwm4. allocated to the primary function of the p44 pin. primary ? t1p5ck i external clock input pin for timer 1 and pwm5. allocated to the primary function of the p45 pin. primary ? *: ml620q15xa have a different pin configuration for eac h package. see ?list of pins? for more details.
fedl620q150a-01 ml620q151a/2a/3a/4a/5a/6a/7a/8a/9a 17/36 pin name i/o description primary/ secondary logic external interrupt exi0 ? 7* i external maskable interrupt input pins. the interrupt is enabled and interrupt edge is selectable by the software for each bit. allocated to the primary function of the p00 to p05 and p30 to p31. primary positive/ negative timer t16ck0 i external clock input pin for 16bit time r 8, timer a and pwm6. allocated to the primary function of the p46 pin. primary ? t16ck1 i external clock input pin for 16bit time r 9, timer b and pwm7. allocated to the primary function of the p47 pin. primary ? tmhaout o 16bit timer a output pin. allocated to the tertiary function of the p22 andn p60. tertiary positive tmhbout o 16bit timer b output pin. allocated to t he tertiary function of the p23 and p61. tertiary positive led drive led0 to led3 o pins for led driving. allocated to the pr imary function of the p20 to p23 pins. primary positive/ negative successive-approximation type a/d converter v ref i reference power supply pin for successive approximation type a/d converter. ? ? ain0 to ain11 i analog inputs to ch0?ch11 of the successive-approximation type a/d converter. allocated to the secondary fu nction of the p30 to p35 and p42 to p47 pins. ? ? analog comparator cmp0p i non-inverting input for comparator0. this pin is used as the primary function of the p41 pin. ? ? cmp0m i inverting input for comparator0. this pin is used as the primary function of the p40 pin. ? ? *: ml620q15xa have a different pin configuration for eac h package. see ?list of pins? for more details.
fedl620q150a-01 ml620q151a/2a/3a/4a/5a/6a/7a/8a/9a 18/36 termination of unused pins how to terminate unused pins pin recommended pin termination reset_n open p14/test0 open test1_n open v ref connect to v dd p00 to p05* connect v dd or v ss p12 connect v dd or v ss p13 open p20 to p23 open p30 to p37* open p40 to p47 open p50 to p57* open p60 to p67* open p70 to p74* open p80 to p87 open *: ml620q15xa have a different pin configuration for eac h package. see ?list of pins? for more details. note: for unused input ports or unused input/output ports, if the corresponding pins are configured as high-impedance inputs and left open, the supply current may become exce ssively large. therefore, it is recommended to configure those pins as either inputs with a pull-down resistor/pull- up resistor or outputs.
fedl620q150a-01 ml620q151a/2a/3a/4a/5a/6a/7a/8a/9a 19/36 electrical characteristics absolute maximum ratings (v ss = 0v) parameter symbol condition rating unit power supply voltage 1 v dd ta = 25 c ? 0.3 to +6.5 v power supply voltage 2 v ddl ta = 25 c ? 0.3 to +2.0 v reference voltage v ref ta = 25 c ? 0.3 to v dd +0.3 v analog input voltage v ai ta = 25 c ? 0.3 to v dd +0.3 v input voltage v in ta = 25 c ? 0.3 to v dd +0.3 v output voltage v out ta = 25 c ? 0.3 to v dd +0.3 v output current 1 i out1 port3,4,5,6,7,8 ta = 25 c ? 12 to +11 ma output current 2 i out2 port2 ta = 25 c ? 12 to +20 ma power dissipation pd ta = 25 c 1 w storage temperature t stg D ? 55 to +150 c recommended operating conditions (v ss = 0v) parameter symbol condition range unit operating temperature t op D ? 40 to +105 c operating voltage v dd D 1.8 to 5.5 v reference voltage v ref D 1.8 to v dd v analog input voltage v ai D v ss to v ref v operating frequency (cpu) f op D 30k to 8.4m hz low-speed crystal oscillation frequency f xtl D 32.768k hz c dl 12 to 25 low-speed crystal oscillation external capacitor c gl use 32.768khz crystal oscillator dt-26 (daishinku corp.) 12 to 25 pf capacitor externally connected to v ddl pin c l D 2.2 30% f
fedl620q150a-01 ml620q151a/2a/3a/4a/5a/6a/7a/8a/9a 20/36 flash memory operating conditions (v ss = 0v) parameter symbol condition range unit data flash memory, at write/erase -40 to +105 operating temperature t op flash rom, at write/erase 0 to +40 c operating voltage v dd at write/erase 1.8 to 5.5 v c epd data flash 10,000 maximum rewrite count c epp program flash 100 times D chip erase all area D program flash 8 kb D block erase data flash 2 kb erase unit D sector erase (data flash only) 1 kb erase time D chip erase, block erase, sector erase 100 ms write unit D D 1 word (2 bytes) D write time (max.) D 1 word (2 bytes) 40 s data retention period y dr D 15 years dc characteristics (oscillation, reset) (v dd =1.8 to 5.5v, v ss =0v, ta= ? 40 to +105 c, unless otherwise specified) parameter symbol conditio n min. typ. max. unit measur ing circuit low-speed crystal oscillation start time* 1 t xtl D D 0.6 2 s ta= +25 c typ -1% 32.768k typ +1% hz ta= -40 to 85 c typ -2.5% 32.768k typ +2.5% hz low-speed rc oscillator frequency f lcr ta= -40 to 105 c typ -3% 32.768k typ +3% hz ta= +25 c typ -5% 2.097 typ +5% mhz high-speed rc oscillator ferequency f hcr ta= -40 c to +105 c typ -15% 2.097 typ +15% mhz pll oscillation frequency f pll lsclk=32.768khz 2,048 clock average typ -1% 8.192 typ +1% mhz reset pulse width p rst D 100 D D reset noise rejection pulse width p nrst D D D 0.4 s 1 power on reset rising time t por D D D 10 ms * 1 : use 32.768khz crystal oscillator dt-26 (daishinku) with capacitance c gl /c dl 12pf.
fedl620q150a-01 ml620q151a/2a/3a/4a/5a/6a/7a/8a/9a 21/36 reset reset pulse width (p rst ) power on reset vdd rising time (t por ) reset_n p rst vil1 vil1 vdd t por 1.8v 0v
fedl620q150a-01 ml620q151a/2a/3a/4a/5a/6a/7a/8a/9a 22/36 dc characteristics (lld) (v dd =2.2 to 5.5v, v ss =0v, ta= ? 40 to +105 c, unless otherwise specified) parameter symbol conditio n min. typ. max. unit meas uring circuit ld1 to 0 = 0h 1.8 1.9 2 ld1 to 0 = 1h 2.45 2.55 2.65 ld1 to 0 = 2h 3.6 3.7 3.8 v d- when power falling ld1 to 0 = 3h 4.1 4.2 4.3 ld1 to 0 = 0h 1.85 1.98 2.1 ld1 to 0 = 1h 2.5 2.63 2.75 ld1 to 0 = 2h 3.65 3.78 3.9 lld threshold voltage v d+ when power rising ld1 to 0 = 3h 4.15 4.28 4.4 v 1 hysterisis v hys D D D 80 D mv ma dc characteristics (analog comparator) (v dd =2.2 to 5.5v, v ss =0v, ta= ? 40 to +105 c, unless otherwise specified) parameter symbol conditio n min. typ. max. unit meas uring circuit cmpnm v in D 0 D v dd -1.4 common mode input voltage cmpnp v in D 0 D v dd v input offset voltage v cmpof D D 5 100 mv response time t cmp cmpnp = cmpnm 100mv D D 1 s 1 dc characteristics (idd) (v dd =1.8 to 5.5v, v ss =0v, ta= ? 40 to +105 c, unless otherwise specified) parameter symbol condit ion min. typ. max. unit meas uring circuit -40 to +35 ? D 1.0 6 supply current 1 idd1 cpu is in stop state. low-speed/high-speed oscillation is stopped. v dd =3.0v -40 to +105 ? D 1.0 22 -40 to +35 ? D 2.5 7 crystal oscillating. cpu is in halt state (ltbc,wbc: operating *2 ). high-speed oscillation is stopped. v dd =3.0v -40 to +105 ? D 2.5 24 -40 to +35 ? D 3.5 9 supply current 2 idd2 internal rc oscillating. cpu is in halt state (ltbc,wbc: operating *2 ). high-speed oscillation is stopped. v dd =3.0v -40 to +105 ? D 3.5 26 -40 to +35 ? D 13 20 supply current 3 idd3 cpu: running at 32khz* 1 high-speed oscillation is stopped. v dd =3.0v -40 to +105 ? D 13 42 a supply current 4 idd4 cpu: running at 2mhz rc oscillating mode* 2 v dd =5.0v D 0.64 2.0 1 supply current 5 idd5 cpu: running at 8.192mhz pll oscillating mode* 2 v dd =5.0v D 5 8 ma * 1 : case when the cpu operating rate is 100% (with no halt state) * 2 : significant bits of blkcon0 to blkcon4 registers are all ?1?.
fedl620q150a-01 ml620q151a/2a/3a/4a/5a/6a/7a/8a/9a 23/36 dc characteristics (vohl, iohl) (v dd =1.8 to 5.5v, v ss =0v, ta= ? 40 to +105 c, unless otherwise specified) parameter symbol conditio n min. typ. max. unit measuring circuit voh1 ioh1 = ? 0.5ma v dd ? 0.5 D D output voltage 1 (p20 to p23) (p30 to p37)* (p40 to p47) (p50 to p57)* (p60 to p67)* (p70 to p74)* (p80 to p87) vol1 iol1 = +0.5ma D D 0.5 iol2 = +10ma v dd 5.0v D D 0.5 output voltage 2 (p20?p23) vol2 when led drive mode is selected iol2 = +8ma v dd 3.0v D D 0.5 iol3 = +3ma v dd 2.0v D D 0.4 output voltage 3 (p40 to p41) (p50 to p51)* (p60 to p61)* (p80 to p81) vol3 when i 2 c mode is selected iol3 = +2ma 2.0v > v dd 1.8v D D vdd* 0.2 v 2 iooh voh = v dd (in high-impedance state) D D 1 output leakage current (p20 to p23) (p30 to p37)* (p40 to p47) (p50 to p57)* (p60 to p67)* (p70 to p74)* (p80 to p87) iool vol = v ss (in high-impedance state) ? 1 D D a 3 dc characteristics (iihl) (v dd =1.8 to 5.5v, v ss =0v, ta= ? 40 to +105 c, unless otherwise specified) parameter symbol conditio n min. typ. max. unit measuring circuit iih1 vih1 = v dd 0 D 1 input current 1 (reset_n) (test1_n) iil1 vil1 = v ss ? 1500 ? 300 ? 20 iih2 vih2 = v dd (when pulled down) 2 30 250 iil2 vil2 = v ss (when pulled up) ? 250 ? 30 ? 2 iih2z vih2 = v dd (in high-impedance state) D D 1 input current 2 (p00 to p05)* (p30 to p37)* (p40 to p47) (p50 to p57)* (p60 to p67)* (p70 to p74)* (p80 to p87) iil2z vil2 = v ss (in high-impedance state) -1 D D a 4
fedl620q150a-01 ml620q151a/2a/3a/4a/5a/6a/7a/8a/9a 24/36 dc characteristics (vihl) (v dd =1.8 to 5.5v, v ss =0v, ta= ? 40 to +105 c, unless otherwise specified) parameter symbol conditio n min. typ. max. unit measuring circuit vih1 D 0.7 v dd D v dd input voltage 1 (reset_n) (p14/test0) (test1_n) (p00 to p05)* (p12, p13) (p30 to p37)* (p40 to p47) (p50 to p57)* (p60 to p67)* (p70 to p74)* (p80 to p87) vil1 D 0 D 0.3 v dd v 5 input pin capacitance (reset_n) (p14/test0) (test1_n) (p00 to p05)* (p12, p13) (p30 to p37)* (p40 to p47) (p50 to p57)* (p60 to p67)* (p70 to p74)* (p80 to p87) cin f = 10khz v rms = 50mv ta = 25 c D D 10 pf D *: ml620q15x have a different pin configuration for each package. see ?list of pins? for more details.
fedl620q150a-01 ml620q151a/2a/3a/4a/5a/6a/7a/8a/9a 25/36 measuring circuit 1 measuring circuit 2 input pins v vih vil output pins ( *2 ) ( *1 ) v dd v ref v ddl v ss (*1) input logic circuit to determi ne the specified measuring conditions. (*2) measured at the specified output pins. a v dd v ref v ddl c l c v 32.768khz crystal c gl c dl xt0 xt1 c gh v ss c v 2.2f c l 2.2f c gl 12pf c dl 12pf 32.768khz crystal oscillator (dt-26 daishinku corp.)
fedl620q150a-01 ml620q151a/2a/3a/4a/5a/6a/7a/8a/9a 26/36 measuring circuit 3 measuring circuit 4 a *3: measured at the specified input pins. (*3) v dd v ref v ddl v ss output pins input pins input pins a vih vil (*1) input logic circuit to determi ne the specified measuring conditions. (*2) measured at the specified output pins. ( *2 ) (*1) v dd v ref v ddl v ss output pins
fedl620q150a-01 ml620q151a/2a/3a/4a/5a/6a/7a/8a/9a 27/36 measuring circuit 5 vih vil *1: input logic circuit to determine the specified measuring conditions. v dd v ref v ddl v ss waveform monitoring output pins input pins (*1)
fedl620q150a-01 ml620q151a/2a/3a/4a/5a/6a/7a/8a/9a 28/36 ac characteristics (external interrupt) (v dd =1.8 to 5.5v, v ss =0v, ta= ? 40 to +105 c, unless otherwise specified) parameter symbol conditio n min. typ. max. unit external interrupt disable period t nul interrupt: enabled (mie = 1), cpu: nop operation 2.5 lsclk D 3.5 lsclk s t nul exi0 to exi7 (rising-edge interrupt) exi0 to exi7 (falling-edge interrupt) exi0 to exi7 (both-edge interrupt) t nul t nul
fedl620q150a-01 ml620q151a/2a/3a/4a/5a/6a/7a/8a/9a 29/36 ac characteristics (synchronous serial port) (v dd =1.8 to 5.5v, v ss =0v, ta= ? 40 to +105 c, unless otherwise specified) parameter symbol conditio n min. typ. max. unit high-speed oscillation stopped 10 D D s sck input cycle (slave mode) t scyc during high-speed oscillation 500 D D ns sck output cycle (master mode) t scyc D D sck (*1) D sec high-speed oscillation stopped 4 D D s sck input pulse width (slave mode) t sw during high-speed oscillation 200 D D ns sck output pulse width (master mode) t sw D sck (*1) 0.4 sck (*1) 0.5 sck (*1) 0.6 sec sout output delay time (slave mode) t sd D D D 180 ns sout output delay time (master mode) t sd D D D 80 ns sin input setup time (slave mode) t ss D 80 D D ns sin input setup time (master mode) t ss D 240 D D ns sin input hold time t sh D 80 D D ns *1: clock period selected by snck3?0 of the serial port n mode register (sionmod1) t sd sckn* sinn* soutn *: indicates the secondary function of the corresponding port. t sd t ss t sh t sw t sw t scyc
fedl620q150a-01 ml620q151a/2a/3a/4a/5a/6a/7a/8a/9a 30/36 ac characteristics (i2c bus interface: standard mode 100khz) (v dd =1.8 to 5.5v, v ss =0v, ta= ? 40 to +105 c, unless otherwise specified) rating parameter symbol condition min. typ. max. unit scl clock frequency f scl ? 0 ? 100 khz scl hold time (start/restart condition) t hd:sta ? 4.0 ? ? s scl ?l? level time t low ? 4.7 ? ? s scl ?h? level time t high ? 4.0 ? ? s scl setup time (restart condition) t su:sta ? 4.7 ? ? s sda hold time t hd:dat ? 0 ? ? s sda setup time t su:dat ? 0.25 ? ? s sda setup time (stop condition) t su:sto ? 4.0 ? ? s bus-free time t buf ? 4.7 ? ? s ac characteristics (i2c bus interface: fast mode 400khz) (v dd =1.8 to 5.5v, v ss =0v, ta= ? 40 to +105 c, unless otherwise specified) rating parameter symbol condition min. typ. max. unit scl clock frequency f scl ? 0 ? 400 khz scl hold time (start/restart condition) t hd:sta ? 0.6 ? ? s scl ?l? level time t low ? 1.3 ? ? s scl ?h? level time t high ? 0.6 ? ? s scl setup time (restart condition) t su:sta ? 0.6 ? ? s sda hold time t hd:dat ? 0 ? ? s sda setup time t su:dat ? 0.1 ? ? s sda setup time (stop condition) t su:sto ? 0.6 ? ? s bus-free time t buf ? 1.3 ? ? s scl sda start condition restart condition stop condition t buf t hd:sta t low t high t su:sta t hd:sta t su:dat t hd:dat t su:sto
fedl620q150a-01 ml620q151a/2a/3a/4a/5a/6a/7a/8a/9a 31/36 characteristics of successive approximation type a/d converter (v dd =1.8 to 5.5v, v ss =0v, ta= ? 40 to +105 c, unless otherwise specified) parameter symbol conditio n min. typ. max. unit resolution n D D D 10 bits 2.7v v ref 5.5v ? 4 D +4 2.2v v ref ? 2.7v ? 6 D +6 integral non-linearity error inl 1.8v v ref ? 2.2v ? 10 D +10 2.7v v ref 5.5v ? 3 D +3 2.2v v ref ? 2.7v ? 5 D +5 differential non-linearity error dnl 1.8v v ref ? 2.2v ? 9 D +9 zero-scale error v off ri 5k
? 6 D +6 full-scale error fse ri 5k
? 6 D +6 lsb input impedance r i D D D 5k
a/d operating voltage v ref v ref v dd 2.7 D 5.5 v cpu works in pll oscillation mode sack bit = 0 2.7v v ref 5.5v D 13.5 D conversion time t conv cpu works in pll oscillation mode sack bit = 1 1.8v v ref 5.5v D 43 D s a v dd v ref v ddl v ss analog input 2.2f - r i 5k
a in0 to a in11 1f 0.1f + 2.2f reference voltage
fedl620q150a-01 ml620q151a/2a/3a/4a/5a/6a/7a/8a/9a 32/36 package dimensions ml620q151a/ml620q152a/ml620q153a package dimension (48pin tqfp) notes for mounting the su rface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humid ity absorbed in storage. therefore, before you perform reflow mounting, contact a rohm sales office for the product name, package name, pin number, package code and desired mounting c onditions (reflow method, temperature and times).
fedl620q150a-01 ml620q151a/2a/3a/4a/5a/6a/7a/8a/9a 33/36 ML620Q154A/ml620q155a/ml620q156a package dimension (52pin tqfp) notes for mounting the su rface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humid ity absorbed in storage. therefore, before you perform reflow mounting, contact a rohm sales office for the product name, package name, pin number, package code and desired mounting c onditions (reflow method, temperature and times).
fedl620q150a-01 ml620q151a/2a/3a/4a/5a/6a/7a/8a/9a 34/36 ml620q157a/ml620q158a/ml620 q159a package dimens ion (64pin tqfp) notes for mounting the su rface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humid ity absorbed in storage. therefore, before you perform reflow mounting, contact a rohm sales office for the product name, package name, pin number, package code and desired mounting c onditions (reflow method, temperature and times).
fedl620q150a-01 ml620q151a/2a/3a/4a/5a/6a/7a/8a/9a 35/36 revision history page document no. date previous edition current edition description pedl620q150-01 jul 15, 2014 ? ? preliminary first edition p2-p4 p2-p4 changed english expression for some descriptions. p5-p7 p5-p7 added notes (*) about some pins. p10 p10 corrected pin names of 57pin and 58pin. p11 p11 deleted the 2 nd function of p02 and p03. p13 p13 corrected the tertiary function name of p70 and p71. p15 p15 changed english ex pression for the note(*). p16 p16 corrected description about pw45evn and pw67evn. p17 p17 corrected description about exi0-7 and tmhnout. p18 p18 changed english ex pression for the note(*). p21 p21 added power on reset rising time (t por ). p24 p24 corrected pin name and change english expression for the note(*). pedl620q150-02 aug 14, 2014 p32 p32 added 52pin tqfp package dimension. ? ? formal first edition ? ? z changed the part numbers. (old) ml620q151/152/153/1 54/155/156/157/158/159 (new) ml620q151a/152a/153a/154a/155a/156a/157a/158a/159a 1 1 z made a list of rom size and rewrite cycle. z made a list of the number of interrupt. 3 3 made a list of the number of ports. 4 4 made a list of the kinds of package. fedl620q150a-01 may 7, 2015 16 16 corrected the port name pwmn assigned.
fedl620q150a-01 ml620q151a/2a/3a/4a/5a/6a/7a/8a/9a 36/36 notes 1) the information contained herein is subject to change without notice. 2) although lapis semiconductor is continuously working to improve product reliability and quality, semiconductors can break down and malfunction due to various factors. therefore, in order to prevent personal injury or fire arising from failure, please take safety measures such as co mplying with the derating characteristics, implementing redundant and fire prevention designs, and utilizing backups and fail-safe procedures. lapis semiconductor shall have no responsibility for any damages arising out of the use of our products beyond the rating specified by lapis semiconductor. 3) examples of application circuits, circuit constants and any ot her information contained herein are provided only to illustrate the standard usage and operations of the products.the peripheral conditions must be taken into account when designing circuits for mass production. 4) the technical information specified herein is intended only to show the typical functions of the products and examples of application circuits for the products. no license, expressly or implied, is granted hereby under any intellectual property rig hts or other rights of lapis semiconductor or any third party with respect to the information contained in this document; therefore lapis semiconductor shall have no responsibility what soever for any dispute, concerning such rights owned by third parties, arising out of the us e of such technical information. 5) the products are intended for use in ge neral electronic equipment (i.e. av/oa devices, communication, consumer systems, gaming/entertainment sets) as well as the applications indicated in this document. 6) the products specified in this document are not designed to be radiation tolerant. 7) for use of our products in applications requiring a high degree of reliability (as exemplified below), please contact and consult with a lapis semiconductor re presentative: transportation equipment (i.e. cars, ships, trains), primary communication equipment, traffic lights, fire/crime prevention, safety equipment, medical systems, servers, solar cells, and power transmission systems. 8) do not use our products in applications requiring extremely high reliability, such as aerosp ace equipment, nuclear power control systems, and submarine repeaters. 9) lapis semiconductor shall have no responsibility for any damages or injury arising from non-compliance with the recommended usage conditions and specifications contained herein. 10) lapis semiconductor has used reasonable care to ensure the accuracy of the information contained in this document. however, lapis semiconductor does not warrant that such in formation is error-free and lapis semiconductor shall have no responsibility for any damages arising from any inaccuracy or misprint of such information. 11) please use the products in accordance with any applicable environmental laws and regulations, such as the rohs directive. for more details, including rohs compatibility, please contact a rohm sales office. lapis semiconductor shall have no responsibility for any damages or losses resulting non-com pliance with any applicable laws or regulations. 12) when providing our products and technologies contained in this document to other countries, you must abide by the procedures and provisions stipulated in all applicable ex port laws and regulations, including without limitation the us export administration regulations and the foreign exchange and foreign trade act. 13) this document, in part or in whole, may not be reprinted or reproduced without prior consent of lapis semiconductor. copyright 2015 lapis semiconductor co., ltd. 2-4-8 shinyokohama, kouhoku-ku, yokohama 222-8575, japan http://www.lapis-semi.com/en/

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